Charge pump circuit

ABSTRACT

There is provided a charge pump circuit which can prevent EMI noise of a frequency component independent of an operation clock frequency from occurring at the time of a change from a disable state to an enable state. The charge pump circuit includes a detection signal synchronization circuit which outputs a synchronization detection signal generated by synchronizing a detection signal outputted from a level detection circuit to a clock signal outputted from an oscillator circuit. The synchronization detection signal is used as a pump enable signal, and a first pump capacitance and a second pump capacitance in a pump circuit body are charged and discharged in response to the synchronization detection signal and the clock signal outputted from the oscillator circuit.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2008-75148 filed onMar. 24, 2008 including the specification, drawings and abstract isincorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

The present invention relates to a charge pump circuit for generating avoltage by charging and discharging capacitors.

A flash memory incorporated in a microcomputer chip uses a high voltageduring operation and therefore includes a charge pump circuit togenerate a boosted voltage. The operation of the charge pump circuitrequires a large current consumption from an external power supply, andelectromagnetic interference (EMI) noise caused by the currentconsumption is radiated to the outside of the microcomputer chip.

A high level of radiated EMI noise causes interference with devicesaround the microcomputer chip. Particularly, as for an IC (IntegratedCircuit) used in an audio device or the like, caution needs to beexercised so that the frequency band of EMI noise radiated from themicrocomputer chip does not overlap with the received frequency band ofthe audio device. Multiples of the operation clock frequency of thecharge pump circuit are dominant in frequency components of EMI noisecaused by the operation of the charge pump circuit. Accordingly, theoperation clock frequency of the charge pump circuit is set inconsideration of a frequency band to be restrained in an environmentwhere the IC is used.

In a power supply circuit disclosed in Japanese Unexamined PatentPublication No. 2005-20971, once a comparator detects an excess of areference voltage, the comparator output is not switched thereafterwithin one pulse of a clock signal. This prevents a charge pump fromoperating at high frequencies and prevents the occurrence of noise.

SUMMARY OF THE INVENTION

In the configuration of a conventional charge pump circuit, there is aduration of an operation asynchronous with a clock signal when thecharge pump circuit changes from a disable state to an enable state. Inthe duration of the operation asynchronous with the clock signal, EMInoise of a frequency component independent of the operation clockfrequency of the charge pump circuit occurs. If the frequency componentindependent of the operation clock frequency falls under a frequencyband to be restrained in an environment where the IC is used, there is aproblem of causing interference in the operation of the IC.

It is an object of the present invention to provide a charge pumpcircuit which can prevent EMI noise of a frequency component independentof an operation clock frequency from occurring at the time of a changefrom a disable state to an enable state.

A charge pump circuit according to the invention includes a charge pumpcircuit body, including a plurality of charge transfer elements coupledin series and a plurality of capacitive elements each coupled to acoupling path between adjacent charge transfer elements, which boosts anexternal power supply voltage supplied from an external power supply tothe charge transfer elements by charging and discharging adjacentcapacitive elements alternately and outputs a boosted voltage higherthan the external power supply voltage; a level detection circuit whichcompares the boosted voltage outputted from the charge pump circuit bodywith a predetermined reference voltage and outputs a level detectionsignal according to a comparison result; an oscillator circuit whichoutputs a clock signal in response to the level detection signaloutputted from the level detection circuit; and a detection signalsynchronization circuit which outputs a synchronization detection signalgenerated by synchronizing the level detection signal outputted from thelevel detection circuit to the clock signal outputted from theoscillator circuit, wherein the capacitive elements in the charge pumpcircuit body are charged and discharged in response to the clock signaloutputted from the oscillator circuit and the synchronization detectionsignal outputted from the detection signal synchronization circuit.

Further, a charge pump circuit according to the invention includes aplurality of charge pump circuit bodies, including a plurality of chargetransfer elements coupled in series and a plurality of capacitiveelements each coupled to a coupling path between adjacent chargetransfer elements, which boost an external power supply voltage suppliedfrom an external power supply to the charge transfer elements bycharging and discharging adjacent capacitive elements alternately andoutput a boosted voltage higher than the external power supply voltage;a level detection circuit which compares the boosted voltage outputtedfrom the charge pump circuit bodies with a predetermined referencevoltage and outputs a level detection signal according to a comparisonresult; an oscillator circuit which outputs respective clock signals tothe charge pump circuit bodies in response to the level detection signaloutputted from the level detection circuit; a plurality of detectionsignal synchronization circuits which one-to-one correspond to thecharge pump circuit bodies, the number of detection signalsynchronization circuits being the same as the number of charge pumpcircuit bodies, and output synchronization detection signals generatedby synchronizing the level detection signal outputted from the leveldetection circuit to the respective clock signals outputted from theoscillator circuit to the charge pump circuit bodies, wherein thecapacitive elements in the charge pump circuit bodies are charged anddischarged in response to the clock signals outputted from theoscillator circuit and the synchronization detection signals outputtedfrom the detection signal synchronization circuits.

According to the charge pump circuit of the invention, the capacitiveelements in the charge pump circuit body are charged and discharged inresponse to the clock signal outputted from the oscillator circuit andthe synchronization detection signal outputted from the detection signalsynchronization circuit in synchronization with the clock signal.Consequently, it is possible to prevent the capacitive elements frombeing charged and discharged when the operation of the charge pumpcircuit body changes from a disable state to an enable state in responseto the level detection signal. Accordingly, it is possible tosynchronize the operation of the charge pump circuit body to the clocksignal, including the change from the disable state to the enable state.Therefore, it is possible to prevent the occurrence of EMI noise of afrequency component which is caused by the operation of the charge pumpcircuit body asynchronous with the clock signal at the time of thechange from the disable state to the enable state and is independent ofthe operation clock frequency.

According to the charge pump circuit of the invention, in the chargepump circuit bodies, the capacitive elements are charged and dischargedin response to the clock signals outputted from the oscillator circuitand the synchronization detection signals outputted from the detectionsignal synchronization circuits in synchronization with the clocksignals. Consequently, it is possible to prevent the capacitive elementsfrom being charged and discharged when the operations of the charge pumpcircuit bodies change from a disable state to an enable state inresponse to the level detection signal. Accordingly, it is possible tosynchronize the operations of all the charge pump circuit bodies to theclock signals, including the change from the disable state to the enablestate. Therefore, it is possible to prevent the occurrence of aconsumption current peak caused by pump operations asynchronous with theclock signals at the time of the change from the disable state to theenable state and the occurrence of EMI noise of a frequency componentindependent of the operation clock frequency.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram schematically showing a microcomputer chip 10incorporating a flash memory.

FIG. 2 is a diagram showing the configuration of a charge pump circuit20 which is a premise for the present invention.

FIG. 3 is a timing chart showing the operation timing of the charge pumpcircuit 20 shown in FIG. 2.

FIG. 4 is a graph showing the relationship between the frequency of theconsumption current I_VPP and the strength of the consumption currentI_VPP in a pump circuit body 23 shown in FIG. 2.

FIG. 5 is a diagram showing the configuration of a charge pump circuit60 according to a first embodiment of the invention.

FIG. 6 is a truth table of a detection signal synchronization circuit70.

FIG. 7 is a timing chart showing the operation timing of the detectionsignal synchronization circuit 70.

FIG. 8 is a timing chart showing the operation timing of the charge pumpcircuit 60 shown in FIG. 5.

FIG. 9 is a graph showing the relationship between the frequency of theconsumption current I_VPP and the strength of the consumption currentI_VPP in the pump circuit body 23 shown in FIG. 5.

FIG. 10 is a diagram showing a D flip-flop 75.

FIG. 11 is a diagram showing the configuration of a charge pump circuit80 which is a premise for the invention.

FIG. 12 is a timing chart showing the operation timing of the chargepump circuit 80 shown in FIG. 11.

FIG. 13 is a diagram showing the configuration of a charge pump circuit90 according to a third embodiment of the invention.

FIG. 14 is a timing chart showing the operation timing of the chargepump circuit 90 shown in FIG. 13.

FIG. 15 is a graph showing the relationship between the frequency of theconsumption current I_VPP and the strength of the consumption currentI_VPP in the first to third pump circuit bodies 23A to 23C shown in FIG.13.

DESCRIPTION OF THE PREFERRED EMBODIMENTS <First Premise Technique>

FIG. 1 is a diagram schematically showing a microcomputer chip 10incorporating a flash memory. The microcomputer chip 10 includes a flashmemory 11, a charge pump circuit 12, a power pin 13, and a CPU core 14.The charge pump circuit 12 is provided in the flash memory 11. When thecharge pump circuit 12 operates, EMI noise is radiated to the outside ofthe microcomputer chip 10 from the power pin 13 for supplying a powersupply voltage to the charge pump circuit 12.

Since multiples of the operation clock frequency of the charge pumpcircuit 12 are dominant in frequency components of EMI noise caused bythe operation of the charge pump circuit 12 and radiated from the powerpin 13, the operation clock frequency of the charge pump circuit 12 isset in consideration of a frequency band to be restrained in anenvironment where an IC is used.

Next, before describing a charge pump circuit according to the presentinvention, a charge pump circuit 20 which is a premise for the inventionwill be described. FIG. 2 is a diagram showing the configuration of thecharge pump circuit 20 which is a premise for the invention. The chargepump circuit 20 includes a level detection circuit 21, an oscillatorcircuit 22, and a charge pump circuit body (hereinafter also referred toas a “pump circuit body”) 23.

The level detection circuit 21 includes a first resistor R1, a secondresistor R2, and an operational amplifier 30. One end of the firstresistor R1 is coupled to the pump circuit body 23 described later, andthe other end of the first resistor R1 is coupled to one end of thesecond resistor R2 and the inverting input terminal of the operationalamplifier 30. The other end of the second resistor R2 is coupled to aground. The output terminal of the operational amplifier 30 is coupledto the oscillator circuit 22 and the pump circuit body 23 describedlater.

A voltage (hereinafter referred to as a “divided voltage”) VDIV obtainedby dividing a boosted voltage VP generated by the pump circuit body 23described later at the dividing point between the first resistor R1 andthe second resistor R2 is inputted to the inverting input terminal ofthe operational amplifier 30. A reference voltage VREF is inputted tothe non-inverting input terminal of the operational amplifier 30. Theoperational amplifier 30 compares the divided voltage VDIV with thereference voltage VREF, and outputs a level detection signal(hereinafter also referred to simply as a “detection signal”) DET. Morespecifically, the operational amplifier 30 outputs a signal of a high (Hfor short) level as a detection signal DET if VREF>VDIV, and outputs asignal of a low (L for short) level as a detection signal DET ifVREF≦VDIV. The detection signal DET outputted from the operationalamplifier 30 is supplied to the oscillator circuit 22 and the pumpcircuit body 23 described later.

The oscillator circuit 22 includes a first inverter 40, a secondinverter 41, a third inverter 42, a fourth inverter 43, and a MOStransistor 44. The first, third, and fourth inverters 40, 42, and 43 areinverters, and the second inverter 41 is a clocked inverter. In theoscillator circuit 22, the three-stage inverters, i.e., the second tofourth inverters 41 to 43 configure a ring oscillator. In the ringoscillator, the second to fourth inverters 41 to 43 are coupled inseries, and the input terminal of the first-stage second inverter 41 iscoupled to the output terminal of the third-stage fourth inverter 43.The output terminal of the fourth inverter 43 is coupled to the pumpcircuit body 23 described later. The MOS transistor 44 is an NMOStransistor.

The first inverter 40 and the first-stage second inverter 41 forming thering oscillator are coupled to the operational amplifier 30 in the leveldetection circuit 21. The first inverter 40 is coupled to the gate ofthe MOS transistor 44 and the first-stage second inverter 41 configuringthe ring oscillator. The drain of the MOS transistor 44 is coupled tothe coupling point between the second inverter 41 and the third inverter42, and the source of the MOS transistor 44 is coupled to the ground.

In the oscillator circuit 22, the detection signal DET outputted fromthe level detection circuit 21 is inputted to the first inverter 40 andthe first-stage second inverter 41 configuring the ring oscillator. Thedetection signal DET functions as an enable signal for the oscillatorcircuit 22. The inversion signal of the detection signal DET outputtedfrom the first inverter 40 and the output signal of the fourth inverter43 are inputted to the second inverter 41. The inversion signal of thedetection signal DET outputted from the first inverter 40 is inputted tothe gate of the MOS transistor 44.

In the oscillator circuit 22, the ring oscillator oscillates at afrequency corresponding to the operation frequency of the pump circuitbody 23, and the fourth inverter 43 configuring the ring oscillatoroutputs a clock signal CLK. The clock signal CLK outputted from thefourth inverter 43 is supplied to the second inverter 41 and the pumpcircuit body 23.

The pump circuit body 23 has a two-stage configuration, and includes aninverter 50, a first pump driver 51, a second pump driver 52, a firstpump capacitance 53, a second pump capacitance 54, a first transfer MOStransistor 55, a second transfer MOS transistor 56, and a third transferMOS transistor 57. The first and second pump drivers 51 and 52 are ANDcircuits. The first and second pump capacitances 53 and 54 which arecapacitive elements are capacitors. The first to third transfer MOStransistors 55 to 57 which are charge transfer elements are NMOStransistors.

The input terminal of the inverter 50 is coupled to the output terminalof the fourth inverter 43 in the oscillator circuit 22, and the outputterminal of the inverter 50 is coupled to an input terminal of the firstpump driver 51. An input terminal of the first pump driver 51 is coupledto the output terminal of the operational amplifier 30 in the leveldetection circuit 21. The output terminal of the first pump driver 51 iscoupled to one end of the first pump capacitance 53.

The input terminals of the second pump driver 52 are coupled to theoutput terminal of the fourth inverter 43 in the oscillator circuit 22and the output terminal of the operational amplifier 30 in the leveldetection circuit 21. The output terminal of the second pump driver 52is coupled to one end of the second pump capacitance 54. An externalpower supply is coupled to the first and second pump drivers 51 and 52.

In the pump circuit body 23, a plurality of diode-coupled MOStransistors having the gate and drain coupled together (the first tothird transfer MOS transistors 55 to 57 in this case) are coupled inseries. The drain of the first transfer MOS transistor 55 is coupled toan external power supply VPP. The source of the third transfer MOStransistor 57 is coupled to the first resistor R1 in the level detectioncircuit 21. The other end of the first pump capacitance 53 is coupled toa first pump node P1, and the other end of the second pump capacitance54 is coupled to a second pump node P2. The first pump node P1 is thecoupling point between the source of the first transfer MOS transistor55 and the drain of the second transfer MOS transistor 56. The secondpump node P2 is the coupling point between the source of the secondtransfer MOS transistor 56 and the drain of the third transfer MOStransistor 57.

In the pump circuit body 23, the clock signal CLK outputted from theoscillator circuit 22 is inputted to the inverter 50 and the second pumpdriver 52. The detection signal DET outputted from the level detectioncircuit 21 is inputted, as a pump enable signal PEN functioning as anenable signal for the pump drivers 51 and 52, to the first and secondpump drivers 51 and 52. The first pump driver 51 performs an ANDoperation of the inversion signal of the clock signal CLK supplied fromthe inverter 50 and the detection signal DET supplied from theoperational amplifier 30 in the level detection circuit 21, and outputsa signal representing the operation result. The second pump driver 52performs an AND operation of the clock signal CLK supplied from thefourth inverter 43 in the oscillator circuit 22 and the detection signalDET supplied from the operational amplifier 30 in the level detectioncircuit 21, and outputs a signal representing the operation result.

Thus, in the pump circuit body 23, the first and second pump drivers 51and 52 charge and discharge the first pump capacitance 53 and the secondpump capacitance 54 alternately in synchronization with the clock signalCLK. Accordingly, the first to third transfer MOS transistors 55 to 57transfer electric charges while boosting voltages from the externalpower supply VPP, thus generating a boosted voltage VP. The boostedvoltage VP generated by the pump circuit body 23 is outputted from thesource of the third transfer MOS transistor 57 to the outside of thecharge pump circuit 12, and supplied to the level detection circuit 21.

FIG. 3 is a timing chart showing the operation timing of the charge pumpcircuit 20 shown in FIG. 2. At a time T10, when the level detectioncircuit 21 detects that the level of the boosted voltage VP is less thana predetermined detection level Ld, the detection signal DET is enabled,that is, the detection signal DET changes from the L level to the Hlevel. In response thereto, the pump circuit body 23 and the oscillatorcircuit 22 are enabled. Consequently, in the pump circuit body 23, theoutput N1 of the first pump driver 51 changes from the L level to the Hlevel, and the level of the first pump node P1 increases. Further, thesecond transfer MOS transistor 56 is brought into conduction, andelectric charges are transferred from the first pump node P1 to thesecond pump node P2, so that the level of the second pump node P2increases and the level of the first pump node P1 decreases. There is adelay time T2 from when the oscillator circuit 22 is enabled until whenit outputs the clock signal CLK.

At a time T11 after the elapse of the delay time T2 from the time T10,when the clock signal CLK changes from the L level to the H level, theoutput N2 of the second pump driver 52 changes from the L level to the Hlevel, and the level of the second pump node P2 increases. Further, thethird transfer MOS transistor 57 is brought into conduction, andelectric charges are transferred from the second pump node P2, so thatthe level of the boosted voltage VP increases and the level of thesecond pump node P2 decreases.

Also at the time T11, the output N1 of the first pump driver 51 changesfrom the H level to the L level, and the level of the first pump node P1decreases. Further, the first transfer MOS transistor 55 is brought intoconduction, and electric charges are transferred from the external powersupply VPP to the first pump node P1, so that the level of the firstpump node P1 increases.

At a time T12, when the clock signal CLK changes from the H level to theL level, the output N1 of the first pump driver 51 changes from the Llevel to the H level, and at the same time, the output N2 of the secondpump driver 52 changes from the H level to the L level. Further, thelevel of the first pump node P1 increases, and the level of the secondpump node P2 decreases. The second transfer MOS transistor 56 is broughtinto conduction, and electric charges are transferred from the firstpump node P1 to the second pump node P2, so that the level of the secondpump node P2 increases and the level of the first pump node P1decreases. After that, the operations of the times T11 and T12 arerepeated until the level of the boosted voltage VP reaches thepredetermined detection level Ld.

At a time T14, when the level detection circuit 21 detects that thelevel of the boosted voltage VP is not less than the predetermineddetection level Ld, the detection signal DET is disabled, that is, thedetection signal DET changes from the H level to the L level. Inresponse thereto, the pump circuit body 23 and the oscillator circuit 22are disabled.

The pump circuit body 23 maintains the disable state until the leveldetection circuit 21 detects at a time T15 that the level of the boostedvoltage VP is less than the predetermined detection level Ld. Thus, thepump circuit body 23 repeats the cycle of the enable state and thedisable state between the times T10 and T15, thereby generating thedesired boosted voltage VP.

Next, description will be made of a consumption current I_VPP of theexternal power supply VPP in the operation of the pump circuit body 23.The external power supply VPP supplies a large consumption current whenthe output N1 of the first pump driver 51 or the output N2 of the secondpump driver 52 changes from the L level to the H level to charge thefirst pump capacitance 53 or the second pump capacitance 54. That is, inFIG. 3, pulsed consumption currents I_VPP flow at the times T10 and T15when the detection signal DET changes from the disable state to theenable state, that is, the detection signal DET changes from the L levelto the H level and at the times T11, T12, T13, T16, and T17 when theclock signal CLK changes from the L level to the H level and changesfrom the H level to the L level.

FIG. 4 is a graph showing the relationship between the frequency of theconsumption current I_VPP and the strength of the consumption currentI_VPP in the pump circuit body 23 shown in FIG. 2. In the graph, thehorizontal axis represents the frequency (Hz) of the consumption currentI_VPP, and the vertical axis represents the strength (db) of theconsumption current I_VPP. As shown in FIG. 4, the consumption currentI_VPP has three strength peaks. The frequency of the highest strength is1/T1 which is two times the frequency of the clock signal CLK with whichthe pump circuit body 23 operates. The frequency of the second highestis 1/T0 which stems from an intermission time T0 from when the pumpcircuit body 23 is disabled until when it is next enabled. The frequency1/T0 is generally a low frequency. The frequency of the lowest strengthis 1/T2 which stems from the time period between the times T10 and T11and the time period between the times T15 and T16 in FIG. 3, that is,the delay time T2 between the change of the detection signal DET fromthe disable state to the enable state and the first rising edge of theclock signal CLK. The frequency 1/T2 is a frequency componentindependent of the operation clock frequency of the pump circuit body23. If this frequency component falls under a frequency band to berestrained in an environment where an IC is used, there is a problem ofcausing interference in the operation of the IC.

The frequency component 1/T2 occurs because, at the times T10 and T15 inFIG. 3, the output N1 of the first pump driver 51 changes from the Llevel to the H level at the same time as the detection signal DET isenabled. That is, at the times T10 and T15, the pump circuit body 23performs operations asynchronous with the clock signal CLK, which causesthe frequency component independent of the clock frequency. For thisreason, a configuration shown in FIG. 5 is applied to a charge pumpcircuit according to the invention.

First Embodiment

FIG. 5 is a diagram showing the configuration of a charge pump circuit60 according to the first embodiment of the invention. The configurationand function of the charge pump circuit 60 shown in FIG. 5 are similarto those of the charge pump circuit 20 shown in FIG. 2; therefore, onlythe different sections will be described, and the corresponding sectionsare denoted by the same reference numerals and will not be described.

The charge pump circuit 60 includes the level detection circuit 21, theoscillator circuit 22, the pump circuit body 23, and a detection signalsynchronization circuit 70. The detection signal synchronization circuit70 includes an RS flip-flop (hereinafter also referred to as an “RSFF”)71 and a synchronization inverter 72. The detection signalsynchronization circuit 70 generates, based on the detection signal DEToutputted from the level detection circuit 21, a signal (hereinafterreferred to as a “synchronization detection signal DETSYNC”) in whichthe enable timing of the pump circuit body 23 is synchronized with theclock signal CLK outputted from the oscillator circuit 22, and suppliesthe generated synchronization detection signal DETSYNC as a pump enablesignal PEN to the pump circuit body 23.

The set terminal S of the RSFF 71 is coupled to the output terminal ofthe fourth inverter 43 in the oscillator circuit 22 and the couplingpoint between the input terminal of the inverter 50 and an inputterminal of the second pump driver 52 in the pump circuit body 23. Thereset terminal /R of the RSFF 71 is coupled to the coupling pointbetween the output terminal of the operational amplifier 30 in the leveldetection circuit 21 and the input terminal of the first inverter 40 inthe oscillator circuit 22. The inverting output terminal /Q of the RSFF71 is coupled to the input terminal of the synchronization inverter 72.The output terminal of the synchronization inverter 72 is coupled to aninput terminal of the second pump driver 52 in the pump circuit body 23.

In the charge pump circuit 20 shown in FIG. 2, the detection signal DEToutputted from the operational amplifier 30 in the level detectioncircuit 21 is inputted, as the pump enable signal PEN, to the first andsecond pump drivers 51 and 52 in the pump circuit body 23. On the otherhand, in the charge pump circuit 60 shown in FIG. 5, the detectionsignal DET outputted from the operational amplifier 30 in the leveldetection circuit 21 is inputted to the reset terminal /R of the RSFF71.

In the charge pump circuit 60, the clock signal CLK outputted from thefourth inverter 43 in the oscillator circuit 22 is inputted to theinverter 50 and the second pump driver 52 in the pump circuit body 23,and is also inputted to the set terminal S of the RSFF 71 in thedetection signal synchronization circuit 70.

The logic of a signal outputted from the inverting output terminal /Q ofthe RSFF 71 in the detection signal synchronization circuit 70 isinverted by the synchronization inverter 72, and the signal obtained byinverting the logic is the synchronization detection signal DETSYNC. Thesynchronization detection signal DETSYNC is inputted, as a pump enablesignal PEN functioning as an enable signal for the pump drivers 51 and52, to the first and second pump drivers 51 and 52 in the pump circuitbody 23.

FIG. 6 is a truth table of the detection signal synchronization circuit70. FIG. 7 is a timing chart showing the operation timing of thedetection signal synchronization circuit 70. In the detection signalsynchronization circuit 70, if the detection signal DET inputted to thereset terminal /R of the RSFF 71 is at the L level, the synchronizationdetection signal DETSYNC outputted from the synchronization inverter 72becomes the L level regardless of the clock signal CLK inputted to theset terminal S of the RSFF 71. If the detection signal DET is at the Hlevel and the clock signal CLK is at the H level, the synchronizationdetection signal DETSYNC becomes the H level. If the detection signalDET is at the H level and the clock signal CLK is at the L level, thesynchronization detection signal DETSYNC holds the preceding state.

Thus, the synchronization detection signal DETSYNC outputted from thedetection signal synchronization circuit 70 is generated based on thedetection signal DET and the clock signal CLK, in accordance with thetruth table shown in FIG. 6. In FIG. 7, on the rising edge of thedetection signal DET at a time T20, the clock signal CLK is at the Llevel; accordingly, the synchronization detection signal DETSYNC holdsthe preceding state which is the L level. Next, on the rising edge ofthe clock signal CLK at a time T21, the detection signal DET is at the Hlevel; accordingly, the synchronization detection signal DETSYNC is setto the H level. Further, on the falling edge of the detection signal DETat a time T24, the synchronization detection signal DETSYNC is reset tothe L level. As described above, the rising edge of the synchronizationdetection signal DETSYNC is synchronized with the rising edge of theclock signal CLK.

FIG. 8 is a timing chart showing the operation timing of the charge pumpcircuit 60 shown in FIG. 5. FIG. 9 is a graph showing the relationshipbetween the frequency of the consumption current I_VPP and the strengthof the consumption current I_VPP in the pump circuit body 23 shown inFIG. 5. In the graph, the horizontal axis represents the frequency (Hz)of the consumption current I_VPP, and the vertical axis represents thestrength (db) of the consumption current I_VPP.

First, at a time T30, when the level detection circuit 21 detects thatthe level of the boosted voltage VP is less than the predetermineddetection level Ld, the detection signal DET is enabled, that is, thedetection signal DET changes from the L level to the H level. Inresponse thereto, the oscillator circuit 22 is enabled. Since thesynchronization detection signal DETSYNC outputted from the detectionsignal synchronization circuit 70 is at the L level, the pump circuitbody 23 is not enabled at the time T30.

There is a delay time from when the oscillator circuit 22 is enableduntil when it outputs the clock signal CLK. At a time T31, when theclock signal CLK changes from the L level to the H level, thesynchronization detection signal DETSYNC changes from the L level to theH level. In response thereto, the pump circuit body 23 is enabled, andthereafter operates in synchronization with the clock signal CLK.

At a time T34, when the level detection circuit 21 detects that thelevel of the boosted voltage VP is not less than the predetermineddetection level Ld, the detection signal DET is disabled, that is, thedetection signal DET changes from the H level to the L level, so thatthe oscillator circuit 22 stops. At the same time, the synchronizationdetection signal DETSYNC changes from the H level to the L level, sothat the pump circuit body 23 is disabled.

The pump circuit body 23 maintains the disable state until the leveldetection circuit 21 detects at a time T35 that the level of the boostedvoltage VP is less than the predetermined detection level Ld.

As described above, in this embodiment, the synchronization detectionsignal synchronized with the clock signal CLK for pump operation is usedas the pump enable signal supplied to the pump circuit body 23. That is,the first pump capacitance 53 and the second pump capacitance 54 in thepump circuit body 23 are charged and discharged in response to the clocksignal outputted from the oscillator circuit 22 and the synchronizationdetection signal outputted from the detection signal synchronizationcircuit 70 in synchronization with the clock signal.

Consequently, it is possible to prevent the first and second pumpcapacitances 53 and 54 from being charged and discharged through thefirst and second pump drivers 51 and 52 when the operation of the pumpcircuit body 23 changes from the disable state to the enable state inresponse to the detection signal. Accordingly, it is possible tosynchronize the operation of the pump circuit body 23 to the clocksignal, including the change from the disable state to the enable state.That is, it is possible to operate the pump circuit body 23 in completesynchronization with the clock signal, including the change from thedisable state to the enable state.

Therefore, it is possible to prevent the occurrence of EMI noise of thefrequency component which is caused by the operation of the pump circuitbody asynchronous with the clock signal at the time of the change fromthe disable state to the enable state and is independent of theoperation clock frequency.

Specifically, as shown in FIG. 8, in the consumption current I_VPP ofthe external power supply VPP in this embodiment, consumption currentpulses which occur at the time of the change from the disable state tothe enable state and are asynchronous with the clock signal CLK in theconventional configuration in which the detection signal DET is used asthe pump enable signal do not exist, but only consumption current pulsessynchronized with the rising and falling edges of the clock signalexist.

Accordingly, as seen in FIG. 9, the strength peaks of I_VPP exist onlyat the frequency 1/T1 which stems from the frequency of the clock signalCLK and the frequency 1/T0 which stems from the intermission time T0 ofthe pump, but the frequency component 1/T2 which is conventionallycaused by the operation of the pump circuit body asynchronous with theclock signal CLK at the time of the change from the disable state to theenable state does not occur.

Further, in this embodiment, the detection signal synchronizationcircuit 70 includes the RSFF 71, the level detection signal outputtedfrom the level detection circuit 21 is supplied to the reset terminal /Rof the RSFF 71, the clock signal CLK outputted from the oscillatorcircuit 22 is supplied to the set terminal S, and the synchronizationdetection signal is outputted from the inverting output terminal /Q.That is, the synchronization detection signal is generated as theinversion signal of the /Q output of the RS flip-flop in which the /Rinput is the level detection signal outputted from the level detectioncircuit 21 and the S input is the clock signal outputted from theoscillator circuit 22.

Accordingly, it is possible to achieve the charge pump circuit 60 whichcan synchronize the operation of the pump circuit body 23 to the clocksignal, including the change of the operation of the pump circuit body23 from the disable state to the enable state in response to the leveldetection signal.

Further, by using the RSFF 71 as in this embodiment, it is possible toachieve the detection signal synchronization circuit 70 with a smallernumber of elements than in the use of a D flip-flop 75 described later,thus making it possible to miniaturize the charge pump circuit 60.

Second Embodiment

Next, a charge pump circuit according to the second embodiment of theinvention will be described. The configuration and function of thecharge pump circuit according to this embodiment are similar to those ofthe charge pump circuit 60 shown in FIG. 5; therefore, only thedifferent sections will be described, and the corresponding sections aredenoted by the same reference numerals and will not be described.

FIG. 10 is a diagram showing a D flip-flop 75. In the charge pumpcircuit 60 according to the first embodiment, the detection signalsynchronization circuit 70 is configured with the RSFF 71 and thesynchronization inverter 72. However, in the charge pump circuitaccording to this embodiment, the detection signal synchronizationcircuit is configured with the D flip-flop 75.

The data input terminal D and the reset terminal /R of the D flip-flop(hereinafter also referred to as a “DFF”) 75 are coupled to the couplingpoint between the output terminal of the operational amplifier 30 in thelevel detection circuit 21 and the input terminal of the first inverter40 in the oscillator circuit 22. The clock input terminal CK of the DFF75 is coupled to the output terminal of the fourth inverter 43 in theoscillator circuit 22 and the coupling point between the input terminalof the inverter 50 and an input terminal of the second pump driver 52 inthe pump circuit body 23. The output terminal Q of the DFF 75 is coupledto input terminals of the first and second pump drivers 51 and 52 in thepump circuit body 23.

The detection signal DET outputted from the operational amplifier 30 inthe level detection circuit 21 is inputted to the data input terminal Dand the reset terminal /R of the DFF 75. The clock signal CLK outputtedfrom the fourth inverter 43 in the oscillator circuit 22 is inputted tothe clock input terminal CK of the DFF 75. The synchronization detectionsignal DETSYNC is outputted from the output terminal Q of the DFF 75.

The timing chart of the operation timing of the DFF 75 is the same asthat of the detection signal synchronization circuit 70 shown in FIG. 7.Accordingly, also in the case where the detection signal synchronizationcircuit is configured with the DFF 75, the rising edge of thesynchronization detection signal DETSYNC is synchronized with the risingedge of the clock signal CLK, as in the first embodiment.

As described above, in this embodiment, the detection signalsynchronization circuit is configured with the DFF 75, the leveldetection signal outputted from the level detection circuit 21 issupplied to the data input terminal D and the reset terminal /R of theDFF 75, the clock signal CLK outputted from the oscillator circuit 22 issupplied to the clock input terminal CK, and the synchronizationdetection signal is outputted from the output terminal Q. That is, thesynchronization detection signal is generated as the /Q output of the Dflip-flop in which the D input and the /R input are the level detectionsignal outputted from the level detection circuit 21 and the CK input isthe clock signal outputted from the oscillator circuit 22. Consequently,it is possible to achieve the charge pump circuit which can synchronizethe operation of the pump circuit body 23 to the clock signal, includingthe change of the operation of the pump circuit body 23 from the disablestate to the enable state in response to the level detection signal.

<Second Premise Technique>

To reduce the peak values of the consumption current I_VPP of theexternal power supply VPP during the operation of the pump circuit body23 in the above-described embodiment, there is a method of, with aconfiguration having a plurality of pump circuit bodies 23, operatingthe pump circuit bodies 23 with clock signals having phases shifted.Before describing a charge pump circuit according to the invention withsuch a method, a charge pump circuit 80 which is a premise for theinvention will be described.

FIG. 11 is a diagram showing the configuration of the charge pumpcircuit 80 which is a premise for the invention. The configuration andfunction of the charge pump circuit 80 shown in FIG. 11 are similar tothose of the charge pump circuit 20 shown in FIG. 2; therefore, only thedifferent sections will be described, and the corresponding sections aredenoted by the same reference numerals and will not be described.

The charge pump circuit 80 includes the level detection circuit 21, theoscillator circuit 22, a first pump circuit body 23A, a second pumpcircuit body 23B, and a third pump circuit body 23C. The first pumpcircuit body 23A has a two-stage configuration, and includes an inverter50 a, a first pump driver 51 a, a second pump driver 52 a, a first pumpcapacitance 53 a, a second pump capacitance 54 a, a first transfer MOStransistor 55 a, a second transfer MOS transistor 56 a, and a thirdtransfer MOS transistor 57 a. The first and second pump capacitances 53a and 54 a which are capacitive elements are capacitors. The first tothird transfer MOS transistors 55 a to 57 a which are charge transferelements are NMOS transistors.

The first pump circuit body 23B has a two-stage configuration, andincludes an inverter 50 b, a first pump driver 51 b, a second pumpdriver 52 b, a first pump capacitance 53 b, a second pump capacitance 54b, a first transfer MOS transistor 55 b, a second transfer MOStransistor 56 b, and a third transfer MOS transistor 57 b. The first andsecond pump capacitances 53 b and 54 b which are capacitive elements arecapacitors. The first to third transfer MOS transistors 55 b to 57 bwhich are charge transfer elements are NMOS transistors.

The first pump circuit body 23C has a two-stage configuration, andincludes an inverter 50 c, a first pump driver 51 c, a second pumpdriver 52 c, a first pump capacitance 53 c, a second pump capacitance 54c, a first transfer MOS transistor 55 c, a second transfer MOStransistor 56 c, and a third transfer MOS transistor 57 c. The first andsecond pump capacitances 53 c and 54 c which are capacitive elements arecapacitors. The first to third transfer MOS transistors 55 c to 57 cwhich are charge transfer elements are NMOS transistors.

The inverters 50 a to 50 c, the first pump drivers 51 a to 51 c, thesecond pump drivers 52 a to 52 c, the first pump capacitances 53 a to 53c, the second pump capacitances 54 a to 54 c, the first transfer MOStransistors 55 a to 55 c, the second transfer MOS transistors 56 a to 56c, and the third transfer MOS transistors 57 a to 57 c configuring thefirst to third pump circuit bodies 23A to 23C, function and operate inthe same manner as the inverter 50, the first pump driver 51, the secondpump driver 52, the first pump capacitance 53, the second pumpcapacitance 54, the first transfer MOS transistor 55, the secondtransfer MOS transistor 56, and the third transfer MOS transistor 57configuring the pump circuit body 23 shown in FIG. 2, respectively.

The output terminal of the second inverter 41 in the oscillator circuit22 is coupled to the input terminal of the inverter 50 a and an inputterminal of the second pump driver 52 a in the first pump circuit body23A. The output terminal of the third inverter 42 in the oscillatorcircuit 22 is coupled to the input terminal of the inverter 50 b and aninput terminal of the second pump driver 52 b in the second pump circuitbody 23B. The output terminal of the fourth inverter 43 in theoscillator circuit 22 is coupled to the input terminal of the inverter50 c and an input terminal of the second pump driver 52 c in the thirdpump circuit body 23C.

The output terminal of the operational amplifier 30 in the leveldetection circuit 21 is coupled to the oscillator circuit 22, and isalso coupled to respective input terminals of the first pump drivers 51a to 51 c and respective input terminals of the second pump drivers 52 ato 52 c in the first to third pump circuit bodies 23A to 23C. Therespective sources of the third transfer MOS transistors 57 a to 57 c inthe first to third pump circuit bodies 23A to 23C are coupled in commonto the first resistor R1 in the level detection circuit 21.

A first clock signal CLK1 is outputted from the output terminal of thesecond inverter 41 in the oscillator circuit 22, and inputted to theinverter 50 a and the second pump driver 52 a in the first pump circuitbody 23A. A second clock signal CLK2 is outputted from the outputterminal of the third inverter 42 in the oscillator circuit 22, andinputted to the inverter 50 b and the second pump driver 52 b in thesecond pump circuit body 23B. A third clock signal CLK3 is outputtedfrom the output terminal of the fourth inverter 43 in the oscillatorcircuit 22, and inputted to the inverter 50 c and the second pump driver52 c in the third pump circuit body 23C. The first clock signal CLK1 andthe third clock signal CLK3 are in phase, and the second clock signalCLK2 is in opposite phase to the first and third clock signals CLK1 andCLK3.

The detection signal DET outputted from the operational amplifier 30 inthe level detection circuit 21 is inputted, as a first pump enablesignal PEN1 functioning as an enable signal for the pump drivers 51 aand 52 a, to the first and second pump drivers 51 a and 52 a in thefirst pump circuit body 23A. The detection signal DET outputted from theoperational amplifier 30 in the level detection circuit 21 is inputted,as a second pump enable signal PEN2 functioning as an enable signal forthe pump drivers 51 b and 52 b, to the first and second pump drivers 51b and 52 b in the second pump circuit body 23B. The detection signal DEToutputted from the operational amplifier 30 in the level detectioncircuit 21 is inputted, as a third pump enable signal PEN3 functioningas an enable signal for the pump drivers 51 c and 52 c, to the first andsecond pump drivers 51 c and 52 c in the third pump circuit body 23C.

The boosted voltage VP generated by the first to third pump circuitbodies 23A to 23C is supplied from the respective sources of the thirdtransfer MOS transistors 57 a to 57 c in the first to third pump circuitbodies 23A to 23C to the level detection circuit 21.

FIG. 12 is a timing chart showing the operation timing of the chargepump circuit 80 shown in FIG. 11. At a time T40, when the leveldetection circuit 21 detects that the level of the boosted voltage VP isless than the predetermined detection level Ld, the detection signal DETchanges from the disable state to the enable state, that is, thedetection signal DET changes from the L level to the H level. Inresponse thereto, the first pump driver 51 a in the first pump circuitbody 23A, the second pump driver 52 b in the second pump circuit body23B, and the first pump driver 51 c in the third pump circuit body 23Coperate.

Thus, at the time T40, all the three pump circuit bodies, that is, thefirst to third pump circuit bodies 23A to 23C operate asynchronouslywith the first to third clock signals CLK1 to CLK3; accordingly, thestrength peak value of the consumption current I_VPP at the time T40 islarger than the strength peak values of the consumption current I_VPP atthe time T41 and thereafter. Therefore, there is a problem of notobtaining the effect of reducing the strength peak value of theconsumption current I_VPP by having a plurality of pump circuit bodies.

Further, as in the configuration having one pump circuit body, in theconsumption current I_VPP, the frequency component which stems from thedelay time T5 between the change of the detection signal DET to theenable state and the first rising edge of the clock signal CLK and isindependent of the clock signal CLK exists; therefore, there is aproblem of causing interference in the operation of the IC.

To solve these problems, although as in the first embodiment thesynchronization detection signal DETSYNC in which the enable timing issynchronized with the clock signal CLK can be used as an enable signalfor the pump circuit body, it is necessary to use, as enable signals forthe pump circuit bodies, synchronization detection signals DETSYNCsynchronized with the respective clock signals CLK. For this reason, aconfiguration shown in FIG. 13 is applied to a charge pump circuitaccording to the invention.

Third Embodiment

FIG. 13 is a diagram showing the configuration of a charge pump circuit90 according to the third embodiment of the invention. The configurationand function of the charge pump circuit 90 according to this embodimentare similar to those of the charge pump circuit 80 shown in FIG. 11;therefore, only the different sections will be described, and thecorresponding sections are denoted by the same reference numerals andwill not be described.

The charge pump circuit 90 includes the level detection circuit 21, theoscillator circuit 22, the first pump circuit body 23A, the second pumpcircuit body 23B, the third pump circuit body 23C, a first detectionsignal synchronization circuit 70A, a second detection signalsynchronization circuit 70B, a third detection signal synchronizationcircuit 70C, and an inverter 95.

The first detection signal synchronization circuit 70A includes an RSFF71 a and a synchronization inverter 72 a. The second detection signalsynchronization circuit 70B includes an RSFF 71 b and a synchronizationinverter 72 b. The third detection signal synchronization circuit 70Cincludes an RSFF 71 c and a synchronization inverter 72 c.

The RSFFs 71 a to 71 c and the synchronization inverters 72 a to 72 cconfiguring the first to third detection signal synchronization circuits70A to 70B function and operate in the same manner as the RSFF 71 andthe synchronization inverter 72 configuring the detection signalsynchronization circuit 70 shown in FIG. 5, respectively.

The set terminal S of the RSFF 71 a in the first detection signalsynchronization circuit 70A is coupled to the output terminal of thesecond inverter 41 in the oscillator circuit 22 and the coupling pointbetween the input terminal of the inverter 50 a and an input terminal ofthe second pump driver 52 a in the first pump circuit body 23A. The setterminal S of the RSFF 71 c in the third detection signalsynchronization circuit 70C is coupled to the output terminal of thefourth inverter 43 in the oscillator circuit 22 and the coupling pointbetween the input terminal of the inverter 50 c and an input terminal ofthe second pump driver 52 c in the third pump circuit body 23C.

The output terminal of the third inverter 42 in the oscillator circuit22 and the coupling point between the input terminal of the inverter 50b and an input terminal of the second pump driver 52 b in the secondpump circuit body 23B are coupled to the input terminal of the inverter95. The output terminal of the inverter 95 is coupled to the setterminal S of the RSFF 71 b in the second detection signalsynchronization circuit 70B.

The reset terminals /R of the RSFFs 71 a to 71 c in the first to thirddetection signal synchronization circuits 70A to 70C are coupled to thecoupling point between the output terminal of the operational amplifier30 in the level detection circuit 21 and the input terminal of the firstinverter 40 in the oscillator circuit 22.

In the charge pump circuit 90, the first clock signal CLK1 outputtedfrom the second inverter 41 in the oscillator circuit 22 is inputted tothe inverter 50 a and the second pump driver 52 a in the first pumpcircuit body 23A, and is also inputted to the set terminal S of the RSFF71 a in the first detection signal synchronization circuit 70A. Thelogic of a signal outputted from the inverting output terminal /Q of theRSFF 71 a is inverted by the synchronization inverter 72 a, and thesignal obtained by inverting the logic is a first synchronizationdetection signal DETSYNC1. The first synchronization detection signalDETSYNC1 is inputted, as a first pump enable signal PEN1 functioning asan enable signal for the pump drivers 51 a and 52 a, to the first andsecond pump drivers 51 a and 52 a in the first pump circuit body 23A.

The third clock signal CLK3 outputted from the fourth inverter 43 in theoscillator circuit 22 is inputted to the inverter 50 c and the secondpump driver 52 c in the third pump circuit body 23C, and is alsoinputted to the set terminal S of the RSFF 71 c in the third detectionsignal synchronization circuit 70C. The logic of a signal outputted fromthe inverting output terminal /Q of the RSFF 71 c is inverted by thesynchronization inverter 72 c, and the signal obtained by inverting thelogic is a third synchronization detection signal DETSYNC3. The thirdsynchronization detection signal DETSYNC3 is inputted, as a third pumpenable signal PEN3 functioning as an enable signal for the pump drivers51 c and 52 c, to the first and second pump drivers 51 c and 52 c in thethird pump circuit body 23C.

The second clock signal CLK2 outputted from the third inverter 42 in theoscillator circuit 22 is inputted to the inverter 50 b and the secondpump driver 52 b in the second pump circuit body 23B, and is alsoinputted to the inverter 95. A signal outputted from the inverter 95 isinputted to the set terminal S of the RSFF 71 b in the second detectionsignal synchronization circuit 70B. The logic of a signal outputted fromthe inverting output terminal /Q of the RSFF 71 b is inverted by thesynchronization inverter 72 b, and the signal obtained by inverting thelogic is a second synchronization detection signal DETSYNC2. The secondsynchronization detection signal DETSYNC2 is inputted, as a second pumpenable signal PEN2 functioning as an enable signal for the pump drivers51 b and 52 b, to the first and second pump drivers 51 b and 52 b in thesecond pump circuit body 23B.

FIG. 14 is a timing chart showing the operation timing of the chargepump circuit 90 shown in FIG. 13. First, at a time T60, when the leveldetection circuit 21 detects that the level of the boosted voltage VP isless than the predetermined detection level Ld, the detection signal DETis enabled, that is, the detection signal DET changes from the L levelto the H level. In response thereto, the oscillator circuit 22 isenabled. Since the first to third synchronization detection signalsDETSYNC1 to DETSYNC3 outputted from the first to third detection signalsynchronization circuits 70A to 70C are at the L level, none of thefirst to third pump circuit bodies 23A to 23C is enabled at the timeT60.

There are delay times from when the oscillator circuit 22 is enableduntil when it outputs the first to third clock signals CLK1 to CLK3. Ata time T61, when the first clock signal CLK1 changes from the L level tothe H level, the first synchronization detection signal DETSYNC1 changesfrom the L level to the H level. In response thereto, the first pumpcircuit body 23A which operates with the first clock signal CLK1 isenabled, and thereafter operates in synchronization with the first clocksignal CLK1.

At a time T62, when the second clock signal CLK2 changes from the Hlevel to the L level, the second synchronization detection signalDETSYNC2 changes from the L level to the H level. In response thereto,the second pump circuit body 23B which operates with the second clocksignal CLK2 is enabled, and thereafter operates in synchronization withthe second clock signal CLK2.

At a time T63, when the third clock signal CLK3 changes from the L levelto the H level, the third synchronization detection signal DETSYNC3changes from the L level to the H level. In response thereto, the thirdpump circuit body 23C which operates with the third clock signal CLK3 isenabled, and thereafter operates in synchronization with the third clocksignal CLK3.

At a time T68, when the level detection circuit 21 detects that thelevel of the boosted voltage VP is not less than the predetermineddetection level Ld, the detection signal DET is disabled, that is, thedetection signal DET changes from the H level to the L level, so thatthe oscillator circuit 22 stops. At the same time, the first to thirdsynchronization detection signals DETSYNC1 to DETSYNC3 change from the Hlevel to the L level, so that all the pump circuit bodies, that is, thefirst to third pump circuit bodies 23A to 23C are disabled.

The first to third pump circuit bodies 23A to 23C maintain the disablestate until the level detection circuit 21 detects at a time T69 thatthe level of the boosted voltage VP is less than the predetermineddetection level Ld and the detection signal DET is enabled.

FIG. 15 is a graph showing the relationship between the frequency of theconsumption current I_VPP and the strength of the consumption currentI_VPP in the first to third pump circuit bodies 23A to 23C shown in FIG.13. In the graph, the horizontal axis represents the frequency (Hz) ofthe consumption current I_VPP, and the vertical axis represents thestrength (db) of the consumption current I_VPP. The strength peaks ofthe consumption current I_VPP exist only at a frequency 1/T3 which stemsfrom the frequency of the first to third clock signals CLK1 to CLK3 anda frequency 1/T4 which stems from the intermission time T4 of the firstto third pump circuit bodies 23A to 23C.

Accordingly, a frequency component 1/T5 which is conventionally causedby the operations of the first to third pump circuit bodies 23A to 23Casynchronous with the first to third clock signals CLK1 to CLK3 at thetime of the change from the disable state to the enable state does notoccur.

As described above, according to this embodiment, in the first to thirdpump circuit bodies 23A to 23C, the first pump capacitances 53 a to 53 cand the second pump capacitances 54 a to 54 c are charged and dischargedin response to the clock signals outputted from the oscillator circuit22 and the synchronization detection signals outputted from thedetection signal synchronization circuits 70A to 70C in synchronizationwith the clock signals. Consequently, it is possible to prevent thefirst pump capacitances 53 a to 53 c and the second pump capacitances 54a to 54 c from being charged and discharged when the operations of thefirst to third pump circuit bodies 23A to 23C change from the disablestate to the enable state in response to the detection signal.Accordingly, it is possible to synchronize the operations of all thefirst to third pump circuit bodies 23A to 23C to the clock signals,including the change from the disable state to the enable state.

That is, in the case of operating the divided pump circuit bodies 23A to23C with clock signals having phases shifted as in this embodiment, byusing the synchronization detection signals synchronized with therespective clock signals CLK for the pump circuit bodies 23A to 23C asthe pump enable signals for the pump circuit bodies 23A to 23C, it ispossible to operate all the pump circuit bodies 23A to 23C in completesynchronization with the clock signals, including the change from thedisable state to the enable state.

Therefore, as in the first embodiment, it is possible to prevent theoccurrence of the consumption current peak caused by the operations ofthe pump circuit bodies asynchronous with the clock signals at the timeof the change from the disable state to the enable state and theoccurrence of EMI noise of the frequency component independent of theoperation clock frequency.

Specifically, as shown in FIG. 14, in the consumption current I_VPP ofthe external power supply VPP in this embodiment, consumption currentpulses which occur at the time of the change from the disable state tothe enable state and are asynchronous with the clock signals in theconventional configuration in which the detection signal DET is used asthe pump enable signal do not exist, but only consumption current pulsessynchronized with the rising and falling edges of the clock signals CLK1to CLK3 exist. Accordingly, it is possible to prevent the occurrence ofI_VPP peak which is conventionally caused by the asynchronous operationsof the pump circuit bodies at the time of the change from the disablestate to the enable state in response to the detection signal.

The above-described embodiments are merely illustrative, and theconfigurations can be modified within the scope of the invention. Forexample, in the third embodiment, the first to third detection signalsynchronization circuits 70A to 70C are configured with the RSFFs 71 ato 71 c and the synchronization inverters 72 a to 72 c. In addition tosuch a configuration, the first to third detection signalsynchronization circuits 70A to 70C may be configured with DFFs 75 shownin FIG. 10. In the case where the first to third detection signalsynchronization circuits 70A to 70C are configured with the DFFs 75, thesame effect as in the third embodiment can be obtained.

1-3. (canceled)
 4. A charge pump circuit comprising: a plurality ofcharge pump circuit bodies, including a plurality of charge transferelements coupled in series and a plurality of capacitive elements eachcoupled to a coupling path between adjacent charge transfer elements,which boost an external power supply voltage supplied from an externalpower supply to the charge transfer elements by charging and dischargingadjacent capacitive elements alternately and output a boosted voltagehigher than the external power supply voltage; a level detection circuitwhich compares the boosted voltage outputted from the charge pumpcircuit bodies with a predetermined reference voltage and outputs alevel detection signal according to a comparison result; an oscillatorcircuit which outputs respective clock signals to the charge pumpcircuit bodies in response to the level detection signal outputted fromthe level detection circuit; a plurality of detection signalsynchronization circuits which one-to-one correspond to the charge pumpcircuit bodies, the number of detection signal synchronization circuitsbeing the same as the number of charge pump circuit bodies, and outputsynchronization detection signals generated by synchronizing the leveldetection signal outputted from the level detection circuit to therespective clock signals outputted from the oscillator circuit to thecharge pump circuit bodies, wherein the capacitive elements in thecharge pump circuit bodies are charged and discharged in response to theclock signals outputted from the oscillator circuit and thesynchronization detection signals outputted from the detection signalsynchronization circuits.